This content originally appeared on DEV Community and was authored by Hedy
Here’s a complete beginner FPGA project: a blinking LED on the Basys 3 (Xilinx Artix-7) board using Verilog and Vivado. This is a great first step to understand clocking, logic, constraints, and synthesis.
Project: Blinking LED with Verilog on Basys 3
Tools You’ll Need
- Board: Digilent Basys 3 (Artix-7)
- Software: Vivado WebPACK (free)
- HDL: Verilog
Step-by-Step Guide
1. Create New Project in Vivado
- Open Vivado → Create New Project
- Name: blinky
- Choose RTL Project → Enable Verilog
- Select Basys 3 board (Part: xc7a35tcpg236-1)
2. Write Verilog Code
Create a new source file: blinky.v
verilog
module blinky (
input wire clk, // 100 MHz clock from Basys 3
output wire led // Connect to one LED
);
reg [23:0] counter = 0; // 24-bit counter for clock division
always @(posedge clk) begin
counter <= counter + 1;
end
assign led = counter[23]; // Blink rate depends on bit position
endmodule
3. Write XDC Constraints File
Create a file blinky.xdc and uncomment the relevant lines for clock and LED:
tcl
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
## LED output
set_property PACKAGE_PIN U16 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports led]
W5 is the 100 MHz clock input, U16 is LED0 on the board.
4. Add Files and Run Synthesis
Add blinky.v and blinky.xdc to the project.
Go to Flow Navigator → Run:
- Synthesis
- Implementation
- Generate Bitstream
5. Program the FPGA
- Connect your Basys 3 board via USB.
- Open Hardware Manager
- Auto-connect → Program Device → Select the .bit file
- Click Program
The LED should now blink slowly!
Modify the Blink Speed
Change counter[23] to counter[25] or counter[21] to make the blink slower or faster.
What You Learned
- Writing Verilog
- Clock division
- Using flip-flops and registers
- Assigning pins with a constraints file
- Synthesizing and programming an FPGA
This content originally appeared on DEV Community and was authored by Hedy